The speed and reliability performance of the leading-edge semiconductor chips fabricated using the 0.25 .mu..OMEGA. technology nodes and beyond is limited by on-chip interconnects. For instance, the maximum clock frequencies of the state-of-the-art microprocessor chips are limited by the on-chip interconnect signal cross-talk and propagation delays due to parasitic elements of the interconnect structure, such as parasitic resistive, capacitive, and inductive elements of the interconnect metallization and dielectric structure. To reduce these parasitic elements and their undesirable effects, industry has turned to alternative materials for forming multi-level interconnects.
The primary approach pursued by the semiconductor industry is to replace conventional interconnect metallization materials, such as aluminum, aluminum alloys and tungsten, with copper due to its higher electrical conductivity (copper resistivity of .ltoreq.2 .mu..OMEGA..multidot.cm vs. Aluminum alloy resistivity of .ltoreq.2.7 .mu..OMEGA..multidot.cm). Another approach is to replace the conventional silicon oxide inter-level dielectric (ILD) and inter-metal dielectric (IMD) layers with reduced permittivity or low-k dielectric. These low-k dielectrics generally complicate interconnect process integration due to their inferior thermal stability as well as their electrical, mechanical and thermal conductivity properties compared to silicon dioxide.
Although, over the next several years, copper is expected to become the material of choice for use in most high-performance logic applications, a number of difficulties exist with the deposition and integration of copper. For instance, due to the technological and manufacturing difficulties associated with dry etching of copper, the primary approach for copper deposition to fill inlaid lines and plugs of a substrate formation are the single and dual damascene techniques which eliminate the need for metal etch processes.
Typically, the dual damascene techniques involves two micro lithography patterning steps and two anisotropic dielectric etching steps to form interconnect via holes, for supporting inter-level metal connections, and to form the dielectric trench pattern, for supporting inlaid copper metallization lines. A thin diffusion barrier layer is generally deposited before copper deposition to prevent copper diffusion and poisoning of the silicon devices during the remaining fabrication steps and during the actual chip operation. A copper layer is then generally deposited as a blanket layer covering not only the line trenches and via holes, but also the remainder of the substrate, including the substrate field regions. Chemical-mechanical polishing (CMP) is then used to remove excess copper, polishing back the copper metal to expose the underlying substrate (e.g., field dielectric regions) and to establish the inlaid metal lines and plugs. This process sequence is generally repeated for each interconnect level until the multi-level interconnect fabrication process flow is complete.
Damascene techniques for formation of inlaid metallization structures have a number of disadvantages due to fabrication process complexities. One significant disadvantage is the need for chemical-mechanical polishing (CMP) which is used to polish back and remove excess metal over the field regions to establish a generally flat or globally planarized surface in conjunction with an inlaid metallization structure. Chemical-mechanical polishing, or CMP, increases the cost and complexity of the interconnect fabrication process.
CMP involves the application of mechanical force through pads in the presence of a suitable slurry (typically applied through holes in the pad) to wear down metal deposited on a substrate while the inlaid metal structures are left relatively intact. This process generates slurry wet chemical waste that needs expensive treatment for disposal and requires frequent replacement of consumable pads. The CMP processes may generate and leave additional residual contaminants and particles on the wafers, thus, producing the need for post-CMP wafer cleaning.
Another difficulty with CMP is that it requires extensive process optimization to prevent or minimize problems such as dishing. Unless the CMP process is optimized in order to meet the process integration requirements, it can reduce the overall chip manufacturing yield and increase the chip production costs. Moreover, the CMP processes require relatively expensive (e.g., over $1-2 million) production equipment, resulting in additional increases in the overall semiconductor factory cost. Chemical-mechanical polishing processes are not easily integrated with copper and barrier deposition processes, resulting in increased chip manufacturing cost and production cycle time for fabrication of chips with copper wiring. For instance, the CMP-based removal rates of tantalum-based barrier materials (such as tantalum and tantalum nitride) are typically much slower than the copper removal rates, resulting in possible metal dishing problems and yield loss. Also, chemical-mechanical polishing is difficult to use with low-k dielectrics.
Another difficulty associated with damascene interconnect techniques relates to the deposition pattern for the copper within a device formation. For instance, copper deposited by chemical-vapor deposition (CVD) for filling of trenches and holes tends to form simultaneously and conformally on the bottom and sides of the formation. This tends to result in a circular grain pattern, and can form a gap or seam within the filling material of the formation due to the convergence of material deposited on the opposite sides of the interconnect trenches and via holes. The smaller grain size of the filling material for a blanket copper fill process and the resulting possible voids or seams can result in manufacturing yield loss and interconnect reliability degradations.